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Computing Platforms for Software-Defined Radio by Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia

By Waqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia

This ebook addresses Software-Defined Radio (SDR) baseband processing from the pc structure viewpoint, supplying a close exploration of other computing structures by way of classifying various methods, highlighting the typical positive factors on the topic of SDR necessities and by means of displaying execs and cons of the proposed recommendations. It covers architectures exploiting parallelism by way of extending single-processor surroundings (such as VLIW, SIMD, TTA approaches), multi-core systems dispensing the computation to both a homogeneous array or a collection of specialised heterogeneous processors, and architectures exploiting fine-grained, coarse-grained, or hybrid reconfigurability.

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The width of the instruction memory is set to 256 bits. The EX-DC control bypass is disabled as proposed in our previous work [17]. The basic RISC-like configuration that consists of one ALU, MAC, and LD/ST unit has an area requirement of 0:144 mm2 and a power consumption of 21,243 mW. 0 V, 125 ı C. 44 G. Sievers et al. Fig. 7 Area requirements of CoreVA CPU configurations with varying number of slot (S, M, L = number of slots, MAC, LD/ST) As depicted in Fig. 7, the area increase for every additional VLIW slots is about 0:032 mm2 .

In addition, the MPSoC features four Fast Fourier Transform (FFT), three channel decoding, and two bit-level hardware accelerators. 3 GOPS. 8 MBit/s throughput. Noethen et al. [24] present Tomahawk2, a heterogeneous MPSoC with 20 CPU cores targeting 4 4 MIMO LTE baseband SDR. The hierarchical MPSoC contains two CPU clusters with four general purpose CPUs (Duo-PE) each and two additional CPU clusters with I/O interfaces, memory controller, and applicationspecific cores. A Duo-PE consists of a fourfold 16 bit SIMD5 core and a Tensilica LX4 CPU with floating-point support.

Therefore, this section analyzes the resource requirements for different processor, cluster, and NoC configurations in terms of area and power consumption. The results are generated using a highly automated standard-cell design-flow based on Cadence Encounter Digital Implementation System. A 28 nm FD-SOI standard-cell library11 provided by STMicroelectronics is used for the physical implementation. This technology offers a maximum clock frequency of 900 MHz for our CPU core. For the proposed implementation we chose a slightly relaxed clock frequency of 800 MHz.

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