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Autonomous software-defined radio receivers for deep space by Jon Hamkins, Marvin K. Simon, Joseph H. Yuen

By Jon Hamkins, Marvin K. Simon, Joseph H. Yuen

This ebook introduces the reader to the concept that of an self sufficient software-defined radio (SDR) receiver. every one designated point of the layout of the receiver is taken care of in a separate bankruptcy written by means of a number of prime innovators within the box. Chapters commence with an issue assertion after which supply a whole mathematical derivation of an acceptable answer, a call metric or loop-structure as applicable, and function effects.

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We briefly summarize the status of the design and analysis of some of these estimators below. 1 Carrier Phase Tracking In autonomous radio operation, it is desired that the receiver contain a carriersynchronization structure that is generic in the sense that it is capable of tracking the carrier phase independently of the modulation. If the modulation is restricted to the M -PSK class, then it is possible to construct a universal structure that performs the carrier-synchronization function for all values of M .

Using conventional estimation and tracking designs, one quickly gets into a chicken and egg problem, with nearly every estimator needing the output of the other estimators before it can make a maximum-likelihood (ML) estimate. To resolve this problem, we have arranged the estimators/classifiers in the partially ordered set shown in Fig. 1-3, which defines the order in which they may be operated, at least sub-optimally, during the first iteration of estimation. Details about the order of estimation and the interaction of the estimators in the first and subsequent iterations are discussed in Chapter 11.

1 AGC The AGC controls the voltage level input to the ADC based on a control voltage signal generated digitally in the FPGA. In particular, the AGC is based on a single feedback control loop design with the AGC control voltage extending back from the carrier-tracking loop (CTL) arm-filter outputs, as indicated in Fig. 2-2. The digital AGC error signal, EAGC , is generated from the CTL armfilter outputs, I and Q, via EAGC = Kgain · (1 − I 2 + Q2 ) (2 1) where Kgain controls the time constant of the AGC as well as the variance of the resulting amplitude gain estimate.

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