By John G. Webster (Editor)
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Extra resources for 11.Components, Packaging, and Manufacturing Technology
The logic swing is the difference between the potentials of signals in high and low logic state. The rise time is the time needed for the signal to pass through the central 80% of the logic swing in transition from the low to the high logic state. Falling time is analogously defined for the falling signal and is usually assumed to be equal to the rise time. Static noise tolerance is determined from the transfer curve of the receiving gate as the smaller difference between the input voltage corresponding to the switching threshold and the logic high value NTH or low value NTL of input signal (Fig.
At the frequency of 8 GHz, the ohmic loss tangent in the same material drops one order of magnitude below the polarization loss tangent. Effect of Dielectric Losses on Modeling. Considering admittance Y ϭ jͶC related to structure capacitive effects with capacitance C ϭ ⑀rC0, we obtain Y = ω r C0 + jω rC0 which indicates clearly that dielectric losses are modeled by the conductance to the ground g(Ͷ) ϭ Ͷ⑀rЉC0 and capacitance CL(Ͷ) ϭ ⑀rЈCo. 360 CIRCUIT ANALYSIS COMPUTING OF SEMICONDUCTOR PACKAGES AND SYSTEMS Imperfect Conductors.
Computation of those matrices involves solution of steady-state electromagnetic fields imposed by the sinusoidal current sources Ik(t) ϭ Ik cos(Ͷt ϩ k) appropriately connected to the conducting traces. The inductances are defined by the principle of equivalency of magnetic energy stored in the model and the actual structure yielding ii = 4uii Ii2 f max = where uii is the magnetic energy stored in the system when the ith conductor is driven and all others are left open and ij = 2uij − uii − ujj Ii I j where uij is the magnetic energy stored in the structure when ith and jth conductors are driven by the current source of amplitudes Ii and Ij, respectively, and the remaining ones are open.